NAND two values and watch the AND resolve before the inversion lands on top of it. Then take the second panel and build any other gate you like out of nothing but NAND.
Two operands, one register width, and both steps shown separately.
Pick a target gate. The schematic rewires itself, and the pins stay live so you can trace a signal through.
NAND is AND with the answer turned around. Give it two 1s and you get 0. Give it anything else and you get 1. That one inversion is why a single NAND gate stands in for every other gate in digital logic, and why a fab that knows how to print NAND gates knows how to print a processor.
Bitwise AND and OR do not care how wide you say the register is. NAND does, and getting this wrong is the most common reason a NAND result looks broken when the arithmetic was fine.
The operation runs in two passes. First it ANDs the operands column by column. Then it inverts every column in the register, not only the columns your operands reached. Any column above your data holds 0 after the AND, so the inversion switches all of them on.
Run 1010 NAND 1100 at four bits and you get 0101. Run the same two operands at thirty two bits and you get twenty eight leading ones in front of that same 0101. Both answers are correct. They answer different questions, because a bit pattern has no width until you name one.
The strip under the result prints the same operation at 4, 8, 16, and 32 bits side by side so the difference stays in front of you. Set the width to match the thing you are targeting: a uint8_t in C, a byte in a protocol field, a 32 bit hardware register.
NAND is functionally complete. Any boolean function of any size is buildable from NAND gates and nothing else. Henry Sheffer proved this in 1913, decades before anyone etched one in silicon, which is why the operation is also written as the Sheffer stroke.
The builder above draws the standard construction for each target and lets you push a signal through it. Watch the XOR network in particular: G1 feeds both middle gates rather than being duplicated, and that shared wire is the whole reason the count stops at four.
| Target | NAND gates | How the wiring goes |
|---|---|---|
| NOT A | 1 | Both inputs tied to the same wire |
| Buffer | 2 | Two inverters back to back |
| A AND B | 2 | NAND, then invert the output |
| A OR B | 3 | Invert both inputs, then NAND the pair |
| A NOR B | 4 | The OR network with a fourth gate inverting it |
| A XOR B | 4 | One shared gate feeding two, then a final merge |
| A XNOR B | 5 | XOR plus an inverter |
Those counts assume two input NAND gates and no sharing between separate outputs. A synthesis tool given a whole design will beat them, because it factors subexpressions across the entire netlist instead of one gate at a time.
A two input NAND in static CMOS is four transistors: two n-channel devices in series to ground, two p-channel devices in parallel to the supply. An AND gate is that same NAND followed by an inverter, so six. OR costs six for the same reason, since it is a NOR with an inverter behind it.
Inverting gates are the cheap primitives. The non-inverting ones are built by paying for an extra stage. This is why a netlist for a design written entirely in ANDs and ORs comes back full of NANDs and NORs with the polarity pushed around by De Morgan's law.
Between the two cheap gates, NAND usually wins on speed. Its series transistors are n-channel, and electrons move through n-channel devices faster than holes move through p-channel ones. A NOR gate puts its p-channel devices in series instead, so it has to make them physically wider to keep up. Standard cell libraries lean on NAND accordingly.
Feed the output of one NAND back into an input of a second, and the second back into the first. The pair stops being combinational. It holds a bit.
That is the SR latch, and the NAND version has active low inputs. Pull S low to set, pull R low to reset, leave both high and the stored bit stays put. Pull both low at once and both outputs go high, which breaks the promise that Q and its complement are opposites. Datasheets call that the forbidden state, and what the latch settles into when you release it depends on which input rises first.
Every flip flop, every static RAM cell, every register in a CPU traces back to this arrangement. The builder above cannot draw it: evaluating a network needs a graph with no cycles, and a latch is a cycle by definition.
NAND flash is named after the gate, but it does not compute a NAND on your data. The naming comes from how the cells are wired.
In NAND flash, several dozen cells sit in series in one string between a bit line and ground. Current flows only when every cell in the string conducts, and that series arrangement matches the pull down network inside a NAND gate. NOR flash hangs its cells in parallel off the bit line instead, matching a NOR pull down.
The layout drives the tradeoff. NAND packs cells tighter and reads them a page at a time, which suits SSDs and memory cards. NOR gives you random access at byte level, which suits firmware that executes in place. Neither one runs a boolean operation on what you store.
Swapping A and B changes nothing. Regrouping a chain changes everything, and this catches people who are used to AND and OR letting them drop the brackets.
Take A = 1, B = 1, C = 0. Group to the left and (1 NAND 1) NAND 0 becomes 0 NAND 0, which is 1. Group to the right and 1 NAND (1 NAND 0) becomes 1 NAND 1, which is 0. Same three values, opposite answers.
Any NAND chain longer than two operands has to state its grouping, so the calculator above takes two at a time on purpose rather than accepting a list and picking an order for you. Feed the result back in as operand A to continue a chain left to right.
You write it as an AND followed by a complement, and the trap is always the same: the complement operator works on the full machine word, not on the handful of bits you were thinking about.
| Language | Written as | What bites |
|---|---|---|
| C, C++ | ~(a & b) | The result widens to an int, so mask it back down with & 0xFF for a byte |
| Java, C# | ~(a & b) | Byte and short operands widen to a 32 bit signed int before the complement runs |
| JavaScript | ~(a & b) | Operands truncate to 32 bit signed, so anything above 2147483647 comes back negative |
| Python | ~(a & b) & 0xFF | Integers are unbounded and signed, so the complement is negative until you mask it |
| Rust | !(a & b) | The same ! is a logical NOT on bool, and the type fixes the width for you |
| Go | ^(a & b) | Unary ^ is the complement, and binary ^ is XOR |
| Verilog | ~(a & b) | ~& looks similar but is reduction NAND across the bits of one vector, giving a single bit |
| VHDL | a nand b | The one language with a real keyword, since it describes hardware where NAND is a primitive |
The two lines land on the same byte here because the assignment truncates. Change bad to an int and it holds 0xFFFFFF7D instead. Write the mask even when you can get away without it, since the next person to widen that variable will not go looking for a missing one.
Where this tool stops
Unsigned integers up to 32 bits, two operands, combinational logic only. Negative decimals are rejected rather than converted, since two's complement depends on a width nobody has confirmed yet: convert first with the number base converter and paste the unsigned pattern in. There is no expression parser, so a mixed line like (a NAND b) & ~c takes more than one pass, and the bitwise calculator covers the other operators. Feedback loops, the thing that makes NAND interesting in real circuits, cannot be drawn in the builder at all. Gate counts there are the textbook constructions, not what a synthesis tool emits after optimization.
Four rows sit in the working area: operand A, operand B, the AND that runs first, and the NAND that falls out of it. Columns come in groups of four to match a hex digit, and the ruler along the top marks every fourth bit position.
The row worth staring at is A AND B. Every column that reads 1 there ends up 0 in the answer, and every column that reads 0 ends up 1. Once that swap is obvious, NAND stops feeling like a separate operation and starts feeling like AND read from the other side.
The four output chips give you the same value in binary, hex, decimal, and octal. Hex is padded to the register width, so an 8 bit result always shows two digits and a 32 bit result always shows eight. Decimal is left unpadded, since leading zeros mean nothing there.
Width behaviour, gate counts, the universal gate claim, and the naming confusion around flash memory.
It outputs 0 only when both inputs are 1. Every other combination gives 1. Read it as AND with the answer inverted, which is where the name comes from: NOT AND.
Because the inversion covers the whole register, not only the columns your operands filled. Columns above your data are 0 after the AND step, so inverting turns every one of them on. A wider register means more of those leading ones. Set the width to match the variable or field you are working with, and the strip under the result shows all four widths at once so the difference stays visible.
Logically yes, and that is the definition. In silicon the relationship runs the other way. A CMOS AND gate is built as a NAND plus an inverter, six transistors against four, so the NAND is the cheaper half of the pair rather than an extra step bolted on.
Because every boolean function can be built from NAND gates alone. Tie both inputs together and you have a NOT. Add an inverter to the output and you have an AND. Invert both inputs and you have an OR. From those three, every other gate follows. NOR is universal for the same reason, and no other two input gate is.
Four in the standard arrangement. The first gate takes both inputs, the second and third each combine one original input with that first output, and the fourth merges them. Five gates is a common answer, and it comes from duplicating the first gate instead of fanning its output out to both middle gates.
No, and that is the trap. With A = 1, B = 1, C = 0, grouping to the left gives 1 and grouping to the right gives 0. Any chain of three or more NANDs has to state its brackets, which is why this calculator handles two operands at a time.
VHDL has a nand keyword because it describes hardware. Verilog has a reduction operator written as a tilde followed by an ampersand, but that ANDs all the bits of one vector and inverts the single result, which is a different job. Everywhere else you write the complement of an AND and mask the result to your intended width.
No. The name describes cell wiring, not computation. NAND flash puts cells in series in a string, so current flows only when they all conduct, which mirrors the series pull down inside a NAND gate. NOR flash wires cells in parallel. The difference shows up as page reads and higher density for NAND against byte level random access for NOR.
Two cross coupled NAND gates form an SR latch with active low inputs. Pulling both inputs low drives both outputs high, so Q and its complement stop being opposites. When you release the inputs, the value the latch lands on depends on which one rises first, and a race that tight is not something a design should rely on.
Both cost four transistors, but the series devices in a NAND are n-channel and the series devices in a NOR are p-channel. Electrons move faster than holes, so a NOR needs wider transistors to match a NAND for speed, and wider means more area and more capacitance. Standard cell libraries are built around that difference.
